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PCI Express 7.0 is on track, up to 512 GB/s bandwidth

Written by Guillaume
Publication date: {{ dayjs(1656259259*1000).local().format("L").toString()}}
This article is an automatic translation

The major companies involved in the development of PCI Express standards have begun work on 7.0.

Last November, Intel was the first to release a platform capable of running PCI Express 5.0, and this, while the specifications for the said standard have been ready since 2019. However, even those with a Z690 motherboard and an Alder Lake processor cannot yet take advantage of the speeds promised by PCI Express 5.0, as no devices are currently available. It's obvious that talking about PCI Express 6.0 - let alone 7.0 - may seem premature... and yet!

The PCI-Special Interest Group (PCI-SIG) has just announced that discussions about the new standard have begun. The idea is to allow the more than 900 IT companies closely or remotely linked to the PCI Express standard to agree on specifications that are both more modern and yet realistic for this version 7.0. The aim is clearly not to achieve this tomorrow, because, as everyone knows, it takes many months of work to bring such a task to a successful conclusion. As an example, PCI Express 5.0 required a little less than two and a half exchanges before being finalized, while PCI Express 6.0 took a little more than two and a half years.

Unsurprisingly, the PCI-SIG is relatively vague about the release date of PCI Express 7.0, but still expects the specifications to be finalized around 2025. At the heart of these specifications, we naturally find the desire to considerably increase the speeds allowed by this interface. The most expert among you may know it, but since the release of PCI Express 4.0, manufacturers manage to maintain a rate of doubling the speed every 3 years.

It is therefore quite logical that for this PCI Express 7.0, the PCI-SIG is aiming for a bandwidth of 128 GT/s per line which, in the case of a x16 link, means a theoretical maximum throughput of 512 GB/s... twice as much as the maximum allowed by the PCI Express 6.0 standard. To achieve such speeds, the PCI-SIG relies on the 4-level pulse amplitude modulation (PAM) which is already in place since PCI Express 6.0. It is also about low latency and better electrical efficiency. Finally, it is of course inevitable that the PCI Express 7.0 standard will be backward compatible.